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fedl67q4060-01 issue date: jan. 21, 2008 ml67q4060/61/50/51 32-bit general-purpose arm-based microcontroller 1/37 overview this lsi is a general-purpose microcontroller that integrates peripheral functions such as i2c, i2s, and various serial interfaces. it uses the arm7tdmitm 32-bit risc cpu developed by arm limited as its core. the following describes the features of the ML67Q4050/ml67q4060 series. features ? cpu atm7tdmi up to 33.33mhz ? internal memory 16kb ram processor bus connection built-in flash rom processor bus connection of the 128kb(ml67q4051 and ml67q4061) or 64kb (ML67Q4050 and ml67q4060) ? external memory controller (function for the ML67Q4050 series only) setting of programmable access timing for each space rom (flash) access function sram access function external i/o access function ? interrupt controller/extended interrupt controller fiq: 1 source (nmi pin) irq: 31 sources (40 sources for the ML67Q4050 series) seven levels of interrupt priorities can be set for each interrupt source. ? system timer 16-bit auto-reload timer: ? 1ch ? sio (uart) full-duplex start-stop synchronization method ? dma controller 2ch ? watchdog timer 16-bit timer ? a/d converter 10-bit sequential comparison type ? 4ch ? i2c bus controller philips i2c bus specification ver 2.1 conformed controller ? flexible timer 16-bit timer ? 6ch operable in each of the modes, auto reload timer (art)/compare out (cmo)/pulse width modulati on (pwm)/capture (cap) ? rtc generates 1 second from 32.768 khz ? i2s transmit/receive connection interface for general-purpose dacs/adcs. conforms to philips i2s (the inter-ic sound) specification ? gpio built-in gpio of 8 bits ? 1ch, 7 bits ? 2ch, and 6 bits ? 3ch ? uart 2 channels of serial communication function with fifo ? spi 2 channel of full duplex serial peripheral interface ? clock main clock oscillator (16 to 33.333mhz) rtc clock oscillator (32.768khz clock) ? power management power saving mode cpu halt mode: stops only the cpu clock. stop mode: stops all the clocks of the chip except rtc ? package 64pin tqfp(tqfp64-p-1010-0.50-k) 84pin lfbga(p-lfbga84-0909-0.80) 64pin wcsp(p-vfbga64-5.09 ? 4.84-0.50-w, p-vflga64-5.09 ? 4.84-0.50-w) 144pin lqfp(lqfp144-p-2020-0.50-zk) 144-pin lfbga (p-lfbga144-1111-0.80)
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 2/37 block diagram ml67q4060 series ad c 4ch uart 2ch i2s i2c spi 2ch ftm 6ch wdt gpio ? 40 rtc bootrom 8kb defslv dmac 2ch cgb sysc system timer sio irc tic imemc arm7tdmi ram 16kb sysc embedded flas h rom 64or128kb flash jtag if ml67q406x ? plat-7b ml67q4060 series block diagram note: ml67q4060: flash rom 64kb ml67q4061: flash rom 128kb
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 3/37 ML67Q4050 series adc 4ch uar t 2ch i2s i2c spi 2ch ftm 6ch wdt gpio ? 108 rtc bootrom 8kb defslv dmac 2ch cg b sysc sy ste m timer sio irc tic pbic arm7tdmi embedded flash rom 64or128kb flas h jtag if ml67q405x ? plat-7b imemc ram 16kb sysc ML67Q4050 series block diagram note: ML67Q4050: flash rom 64kb ml67q4051: flash rom 128kb
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 4/37 pin configuration 144pin lqfp (lqfp144-p-2020-0.50-zk) xa16 xa17 co revdd xa18 iovdd xa19 pllgnd pllgnd xa20 pllvdd pllvdd xa21 rtcclk_n rtcclk_p gnd gnd sysclk_p sysclk_n xa22 pa 0 pa1 pa 2 pa 3 xa 0 iovdd pa4 xd31 xd29 pa 5 xd28 xd27 xd26 corevdd xd25 xd24 xd30 xd8 g nd bootclk xd9 xd10 xd11 pc0 xd12 xd13 iovdd xd15 xd14 pc1 pc2 pc3 pc4 pc5 xd16 resetn g nd g nd rst out _n pc6 pc7 pd4 iovdd xd17 xd18 xd23 xd19 pe5 xd20 xd21 pe6 xd22 g nd xd7 xd6 cor evdd xd5 xd4 xd3 xd2 fl as ht es t gnd exbuse xd1 xd0 pf5 pf4 pf3 pf2 pf 1 pf 0 pe4 pe3 pb2 pb 1 pb0 iovdd bs 0_ n wr _n gnd exirome iovdd bo o t1 iocs1_n iocs0_n ramcs_n corevdd romcs_n oe_n bs1_n gnd bs2_n pb3 bs3_n xa1 xa2 pb4 xa3 xa4 xa5 xa6 pb5 iovdd gnd pe0 pd0 pd1 pd3 pd2 pe1 gnd iovdd pe2 xa7 xa8 xa9 test1 xa10 xa11 xa13 xa12 test 2 xa14 gnd xa15 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 top view index mark
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 5/37 144pin lfbga (p-lfbga144-1111-0. 80) top view 1 2 3 4 5 6 7 8 9 10 11 12 13 a b c d e f g h j k l m n xd23 gnd xd22 pe5 iovdd pc7 pc5 xd15 xd13 xd11 xd8 xd7 boot clk xa16 xa15 xa14 xa12 xa10 xa7 iovdd pb5 xa4 xa2 pb3 gnd bs1_n pa5 sys clk_n sys clk_p rtc clk_p rtc clk_n pa4 pe6 core vdd pll gnd pa3 pa0 test2 pll vdd rst out_n test1 pa2 resetn pc4 pc3 pc0 pf4 pf5 flash test pf2 pe4 pb0 pb4 pf1 pe0 pf3 pb2 pe3 pb1 bs0_n pe2 gnd pd1 pd0 pa1 pf0 xa17 gnd xa13 xa9 pd3 pd2 pe1 iovdd xa6 xa3 xa1 romcs _n oe_n xa18 xa19 xa11 bs3_n bs2_n iocs0 _n core vdd xa20 iovdd xa8 gnd xa5 ramcs _ n boot1 gnd iocs1 _ n xa21 pll gnd pll vdd wr_n iovdd ex irome gnd gnd xa22 iovdd iovdd xd30 xa0 xd29 xd1 xd0 exbuse xd28 xd31 xd26 xd17 xd14 xd9 xd4 gnd xd2 core vdd xd27 xd21 xd19 gnd xd16 xd12 core vdd xd3 xd5 xd24 xd25 xd20 xd18 pd4 pc6 gnd pc2 pc1 iovdd xd10 gnd xd6
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 6/37 64pin tqfp (tqfp64-p-1010-0.50-k) corevdd pllgnd pllvdd rtcclk_n rt cclk_p gnd sy scl k_ p sysclk_n pa 0 pa1 pa 2 pa 3 iovdd pa4 pa 5 co revdd cor evdd flas htest gnd pf 5 pf4 pf3 pf 2 pf1 pf 0 pe4 pe 3 pb2 pb 1 pb0 io vd d cor evdd pb3 pb 4 io vd d pb5 pe0 gnd pe 1 pe 2 gn d iovdd pd 1 pd0 pd2 pd3 test1 t est 2 bo ot cl k pc0 io v d d pc1 pc2 pc4 pc3 pc5 pe 6 resetn gnd rst out _n pc6 pd4 pc7 pe 5 top view index mark 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 4 8 4 7 4 6 4 5 4 4 43 4 2 41 4 0 3 9 3 8 3 7 36 3 5 34 3 3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 7/37 84pin lfbga (p-lfbga84-0909-0.80) top view 1 2 3 4 5 6 7 8 a b c d e f g h j k 9 10 core vdd pll vdd iovdd rtc clk_p sy s clk_p pa1 iovdd pa5 nc gnd nc pll gnd nc pll vdd gnd sys clk_n pa 2 pa 4 core vdd pe 6 nc pll gnd gnd rtc clk_n gnd pa 0 pa 3 io vdd pe 5 p d4 test2 test1 pd3 pc6 pc7 rstout _n pd2 pd1 pd0 gnd gnd resetn iovdd pe2 gnd pc4 pc5 pc3 pe 1 gnd pe0 pc 1 pc2 iovdd iovdd pb5 pb4 gnd pb2 pf0 pf3 iovdd pc0 boot clk pb 3 core vdd nc pb0 pe3 pf1 pf4 gnd gnd nc gnd nc nc iovdd pb1 pe4 pf2 pf5 flash test core vdd
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 8/37 64pin wcsp (p-vfbga64-5.094.84-0.50-w, p-vflga64-5.094.84-0.50-w) top view 1 2 3 4 5 6 7 8 a b c d e f g h pa 5 sys clk_n iov dd sys clk_ p gnd rt c clk_ p rt c clk_n co re vdd pa 4 co re vdd pe6 gnd iov dd co re vdd co re vdd pl l gnd pd4 pa 3 pe5 pa 0 iov dd t est2 gnd pl l vdd rsto ut _n pc7 pc6 test1 pc5 pa2 resetn iov d d pc2 pc4 pc3 pe1 pc0 pf4 gn d iov d d boot clk pf5 fla sh tes t pf2 pe4 pb0 pb4 pb3 pf1 pe3 pb5 pe0 pf3 pb2 pe2 gn d pc1 pb1 pd1 pd0 pa 1 p f 0 p d 2 p d 3
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 9/37 pin descriptions table 1-1 list the functions of all pins in the ML67Q4050/ml67q4060 series. ?i?, ?o?, and ?i/o? in each input/output column signify an input pin, output pin and input/output pin, respectively. ipu stands for ?internally pulled up?.
fedl67q4060-0 ml67q4060/61/50/51 10/37 lapis semiconductor table 1-1 list of ml 67q4050/ml67q4060 series pin functions (1 of 6) primary function secondary function tertiary function setting at reset pin assignment pin name i/o description signal name i/o descriptio n signal name i/o description signal name i/o description ipu schmitt trigger circuit sink current [ma] 144 qfp 144 bga 64 qfp 84 bga 64 wcsp resetn i reset input ? ? ? 54 g4 24 k5 b5 sysclk_p i main clock ?? ? 17b77e1d1 sysclk_n o main clock ?? ? 18d78f2c1 rtcclk_p i rtc clock ?? ? 14b85d1f1 rtcclk_n o rtc clock ? ? ? 13 a8 4 d3 g1 test1 i test pin 1 ? ? ? 137 e11 63 c4 h4 test2 i test pin 2 ? ? ? 141 d10 64 a4 f3 iovdd - i/o power supply ? ? ? *[1] *[6] *[11] *[14] *[19] corevdd - internal power supply ? ? ? *[2] *[7] *[12] *[15] *[20] gnd - gnd ? ? ? *[3] *[8] *[13] *[16] *[21] pllvdd - pll power supply ? ? ? *[4] *[9] 3 *[17] h3 pllgnd - pll gnd ? ? ? *[5] *[10] 2 *[18] h2 flashtest - test pin (nc) ? ? ? 80 l5 34 j10 b8 144qfp *[1] iovdd: 5, 25, 46, 63, 85, 101, 122, 128 *[2] corevdd: 3, 34, 75, 106 *[3] gnd: 15, 16, 38, 52, 53, 71, 81, 99, 110, 124, 126, 143 *[4] pllvdd: 10, 11 *[5] pllgnd: 7, 8 144bga *[6] iovdd: a6, c10, e1, g13, h12, k2, l9, n6 *[7] corevdd: a3, c11, l3, n11 *[8] gdn: b1, b12, c8, d8, f3, g2, g10, h11, m2, m4, m10, m13 *[9] pllvdd: a9, d9 *[10] pllgnd: a10, c9 64qfp *[11] iovdd: 13, 30, 47, 52, 58, *[12] corevdd: 1, 16, 33, 48, *[13] gnd: 6, 23, 35, 54, 56, 84bga *[14] iovdd: a6, a8, b1, g1, h3, h8, k7, d10, *[15] corevdd: a1, c9, j2, k10, *[16] gnd: a10, b3, b6, c7, d8, e2, e3, j5, j9, k1, h5, h9, *[17] pllvdd: c1, d2, *[18] pllgnd: c2, c3, *nc: a2, a3, b2, b9, b10, c10, j1, k9, 64wcsp *[19] iovdd: b1, e2, e3, h5, h7, *[20] corevdd: c2, g2, h1, f2, *[21] gnd: b7, d2, e1, g3, g6,
fedl67q4060-0 ml67q4060/61/50/51 11/37 lapis semiconductor table 1-1 list of ml 67q4050/ml67q4060 series pin functions (2 of 6) primary function secondary function tertiary function setting at reset pin assignment pin name i/o description signal name i/o description signal name i/o description signal name i/o description ipu schmitt trigger circuit sink current [ma] 144 qfp 144 bga 64 qfp 84 bga 64 wcsp pa0 i/o general-purpo se port a0 tck i jtag clock ? ? 3 20 a7 9 f3 d3 pa1 i/o general-purpo se port a1 tms i jtag mode setting ? ? 3 21 c6 10 f1 d4 pa2 i/o general-purpo se port a2 tdi i jtag data input ? ? 3 22 d6 11 g2 c5 pa3 i/o general-purpo se port a3 tdo o jtag data output ? ? 3 23 b6 12 g3 c3 pa4 i/o general-purpo se port a4 ntrs t i jtag reset ? ? 3 26 d5 14 h2 a2 pa5 i/o general-purpo se port a5 jtage i jtag enable ? ? 3 30 c4 15 h1 a1 rstout_n o reset output pa6 i/o general-purp ose port a6 mclk o audio_clk output ? ? 3 51 f4 22 k4 a4 pb0 i/o general-purpo se port b0 tx0 o uart0 tx ? ? 3 96 m9 46 d9 f8 pb1 i/o general-purpo se port b1 rx0 i uart0 rx ? ? 3 95 m8 45 e10 e5 pb2 i/o general-purpo se port b2 tx1 o uart1 tx efiq_n i external interrupt fiq*note ? ? 3 94 k8 44 e8 e6 pb3 i/o general-purpo se port b3 rx1 i uart1 rx exint1 i external interrupt 1 *note ? ? 3 112 l13 49 a9 h8 pb4 i/o general-purpo se port b4 scl i/o i2c scl txd o sio tx ? ? 3 116 j11 50 b8 g8 pb5 i/o general-purpo se port b5 sda i/o i2c sda rxd i sio rx ? ? 3 121 h13 51 c8 f7 pc0 i/o general-purpo se port c0 miso0 i/o spi0 miso dsr0 i uart0 dsr ? ? 3 66 k3 31 j8 a7 pc1 i/o general-purpo se port c1 mosi0 i/o spi0 mosi dtr0 o uart0 dtr ? ? 3 60 j2 29 h7 d5 pc2 i/o general-purpo se port c2 sck0 i/o spi0 sck ri0 i uart0 ri ? ? 3 59 h2 28 j7 a6 pc3 i/o general-purpo se port c3 ssn0 i/o spi0 ssn dcd0 i uart0 dcd ? ? 3 58 h4 27 k6 b6 pc4 i/o general-purpo se port c4 miso1 i/o spi1 miso dsr1 i uart1 dsr ? ? 3 57 h3 26 h6 c6 pc5 i/o general-purpo se port c5 mosi1 i/o spi1 mosi dtr1 o uart1 dtr ? ? 3 56 g1 25 j6 a5 pc6 i/o general-purpo se port c6 sck1 i/o spi1 sck ri1 i uart1 ri ? ? 3 50 f2 21 h4 b4 pc7 i/o general-purpo se port c7 ssn1 i/o spi1 ssn dcd1 i uart1 dcd ? ? 3 49 f1 20 j4 c4 *note: external interrupt fiq and external interrupt 1 can be used as interrupt signals in the primary and secondary functions.
fedl67q4060-0 ml67q4060/61/50/51 12/37 lapis semiconductor table 1-1 list of ml 67q4050/ml67q4060 series pin functions (3 of 6) primary function secondary function tertiary function setting at reset pin assignment pin name i/o description signal name i/o description signal name i/o description signal name i/o description ipu schmitt trigger circuit sink current [ma] 144 qfp 144 bga 64 qfp 84 bga 64 wcsp pd0 i/o general-purp ose port d0 ain0 i analog input 0 exint 2 i external interrupt 2 *note ? ? 3 129 f11 59 b5 g5 pd1 i/o general-purp ose port d1 ain1 i analog input 1 exint 3 i external interrupt 3 *note ? ? 3 130 f10 60 c5 f5 pd2 i/o general-purp ose port d2 ain2 i analog input 2 ? ? 3 131 f12 61 a5 f4 pd3 i/o general-purp ose port d3 ain3 i analog input 3 ? ? 3 132 e12 62 b4 g4 pd4 i/o general-purp ose port d4 bs i boundary scan ? ? 3 48 e2 19 k3 a3 bootcl k i/o general-purp ose port d5 bootclk i boot clock ? ? 3 70 l1 32 k8 a8 pe0 i/o general-purp ose port e0 ? ? 20 123 h10 53 b7 g7 pe1 i/o general-purp ose port e1 ? ? 20 125 g12 55 a7 h6 pe2 i/o general-purp ose port e2 ? ? 20 127 g11 57 c6 f6 pe3 i/o general-purp ose port e3 mclk o audio_cl k output boot0 i boot select 0 ? ? 3 93 l8 43 e9 e7 pe4 i/o general-purp ose port e4 sd i/o i2s sd ? ? 3 92 n7 42 f10 e8 pe5 i/o general-purp ose port e5 ws i/o i2s ws ? ? 3 43 d1 18 j3 b3 pe6 i/o general-purp ose port e6 sck i/o i2s sck ? ? 3 39 c3 17 k2 b2 pf0 i/o general-purp ose port f0 timer0 i/o ftm0 cts0 i uart0 cts ? ? 3 91 l7 41 f8 e4 pf1 i/o general-purp ose port f1 timer1 i/o ftm1 rts0 o uart0 rts ? ? 3 90 k7 40 f9 d7 pf2 i/o general-purp ose port f2 timer2 i/o ftm2 cts1 i uart1 cts ? ? 3 89 m7 39 g10 d8 pf3 i/o general-purp ose port f3 timer3 i/o ftm3 rts1 o uart1 rts ? ? 3 88 l6 38 g8 d6 pf4 i/o general-purp ose port f4 timer4 i/o ftm4 exint 4 i external interrupt 4 *note ? ? 3 87 k6 37 g9 c7 pf5 i/o general-purp ose port f5 timer5 i/o ftm5 exint 5 i external interrupt 5 *note ? ? 3 86 m6 36 h10 c8 *note: external interrupts 2 to 5 can be used as in terrupt signals in the primary and secondary functions.
fedl67q4060-0 ml67q4060/61/50/51 13/37 lapis semiconductor table 1-1 (4/6) list of pin functions of the ML67Q4050/ml67q4060 series that is provided below are applicable to the ML67Q4050 series only. table 1-1 list of ml 67q4050/ml67q4060 series pin functions (4 of 6) primary function secondary function tertiary function setting at reset pin assignment pin name i/o description signal name i/o description signal name i/o description signal name i/o description ipu schmitt trigger circuit sink current [ma] 144 qfp 144 bga 64 qfp 84 bga 64 wcsp xa0 o external address bus 0 pi7 i/o general-purp ose port pi7 ? ? 5 24 b5 ? ? ? xa1 o external address bus 1 pg0 i/o general-purp ose port pg0 ? ? 5 114 l12 ? ? ? xa2 o external address bus 2 pg1 i/o general-purp ose port pg1 ? ? 5 115 k13 ? ? ? xa3 o external address bus 3 pg2 i/o general-purp ose port pg2 ? ? 5 117 k12 ? ? ? xa4 o external address bus 4 pg3 i/o general-purp ose port pg3 ? ? 5 118 j13 ? ? ? xa5 o external address bus 5 pg4 i/o general-purp ose port pg4 ? ? 5 119 j10 ? ? ? xa6 o external address bus 6 pg5 i/o general-purp ose port pg5 ? ? 5 120 j12 ? ? ? xa7 o external address bus 7 pg6 i/o general-purp ose port pg6 ? ? 5 133 f13 ? ? ? xa8 o external address bus 8 ph0 i/o general-purp ose port ph0 ? ? 5 134 e10 ? ? ? xa9 o external address bus 9 ph1 i/o general-purp ose port ph1 ? ? 5 135 d12 ? ? ? xa10 o external address bus 10 ph2 i/o general-purp ose port ph2 ? ? 5 136 e13 ? ? ? xa11 o external address bus 11 ph3 i/o general-purp ose port ph3 ? ? 5 138 d11 ? ? ? xa12 o external address bus 12 ph4 i/o general-purp ose port ph4 ? ? 5 139 d13 ? ? ? xa13 o external address bus 13 ph5 i/o general-purp ose port ph5 ? ? 5 140 c12 ? ? ? xa14 o external address bus 14 ph6 i/o general-purp ose port ph6 ? ? 5 142 c13 ? ? ? xa15 o external address bus 15 ph7 i/o general-purp ose port ph7 ? ? 5 144 b13 ? ? ? xa16 o external address bus 16 pi0 i/o general-purp ose port pi0 ? ? 5 1 a13 ? ? ? xa17 o external address bus 17 pi1 i/o general-purp ose port pi1 ? ? 5 2 a12 ? ? ?
fedl67q4060-0 ml67q4060/61/50/51 14/37 lapis semiconductor primary function secondary function tertiary function setting at reset pin assignment pin name i/o description signal name i/o description signal name i/o description signal name i/o description ipu schmitt trigger circuit sink current [ma] 144 qfp 144 bga 64 qfp 84 bga 64 wcsp xa18 o external address bus 18 pi2 i/o general-purp ose port pi2 ? ? 5 4 a11 ? ? ? xa19 o external address bus 19 pi3 i/o general-purp ose port pi3 ? ? 5 6 b11 ? ? ? xa20 o external address bus 20 pi4 i/o general-purp ose port pi4 ? ? 5 9 b10 ? ? ? xa21 o external address bus 21 pi5 i/o general-purp ose port pi5 dmare q i dma request ? ? 5 12 b9 ? ? ? xa22 o external address bus 22 pi6 i/o general-purp ose port pi6 dmacl r o clear dma request ? ? 5 19 c7 ? ? ?
fedl67q4060-0 ml67q4060/61/50/51 15/37 lapis semiconductor table 1-1 (5/6) list of pin functions of the ML67Q4050/ml67q4060 series that is provided below are applicable to the ML67Q4050 series only. table 1-1 list of ml 67q4050/ml67q4060 series pin functions (5 of 6) primary function secondary function tertiary function setting at reset pin assignment pin name i/o description signal name i/o description signal name i/o description signal name i/o description ipu schmitt trigger circuit sink current [ma] 144 qfp 144 bga 64 qfp 84 bga 64 wcsp xd0 i/o external data bus 0 pj0 i/o general-purp ose port j0 ? ? 5 84 m5 ? ? ? xd1 i/o external data bus 1 pj1 i/o general-purp ose port j1 ? ? 5 83 k5 ? ? ? xd2 i/o external data bus 2 pj2 i/o general-purp ose port j2 ? ? 5 79 n4 ? ? ? xd3 i/o external data bus 3 pj3 i/o general-purp ose port j3 ? ? 5 78 m3 ? ? ? xd4 i/o external data bus 4 pj4 i/o general-purp ose port j4 ? ? 5 77 l4 ? ? ? xd5 i/o external data bus 5 pj5 i/o general-purp ose port j5 ? ? 5 76 n3 ? ? ? xd6 i/o external data bus 6 pj6 i/o general-purp ose port j6 ? ? 5 74 n2 ? ? ? xd7 i/o external data bus 7 pj7 i/o general-purp ose port j7 ? ? 5 73 n1 ? ? ? xd8 i/o external data bus 8 pk0 i/o general-purp ose port k0 ? ? 5 72 m1 ? ? ? xd9 i/o external data bus 9 pk1 i/o general-purp ose port k1 ? ? 5 69 k4 ? ? ? xd10 i/o external data bus 10 pk2 i/o general-purp ose port k2 ? ? 5 68 l2 ? ? ? xd11 i/o external data bus 11 pk3 i/o general-purp ose port k3 ? ? 5 67 k1 ? ? ? xd12 i/o external data bus 12 pk4 i/o general-purp ose port k4 ? ? 5 65 j3 ? ? ? xd13 i/o external data bus 13 pk5 i/o general-purp ose port k5 ? ? 5 64 j1 ? ? ? xd14 i/o external data bus 14 pk6 i/o general-purp ose port k6 ? ? 5 62 j4 ? ? ? xd15 i/o external data bus 15 pk7 i/o general-purp ose port k7 ? ? 5 61 h1 ? ? ? xd16 i/o external data bus 16 pl0 i/o general-purp ose port l0 ? ? 5 55 g3 ? ? ? xd17 i/o external data bus 17 pl1 i/o general-purp ose port l1 ? ? 5 47 e4 ? ? ?
fedl67q4060-0 ml67q4060/61/50/51 16/37 lapis semiconductor primary function secondary function tertiary function setting at reset pin assignment pin name i/o description signal name i/o description signal name i/o description signal name i/o description ipu schmitt trigger circuit sink current [ma] 144 qfp 144 bga 64 qfp 84 bga 64 wcsp xd18 i/o external data bus 18 pl2 i/o general-purp ose port l2 ? ? 5 45 d2 ? ? ? xd19 i/o external data bus 19 pl3 i/o general-purp ose port l3 ? ? 5 44 e3 ? ? ? xd20 i/o external data bus 20 pl4 i/o general-purp ose port l4 ? ? 5 42 c2 ? ? ? xd21 i/o external data bus 21 pl5 i/o general-purp ose port l5 ? ? 5 41 d3 ? ? ? xd22 i/o external data bus 22 pl6 i/o general-purp ose port l6 ? ? 5 40 c1 ? ? ? xd23 i/o external data bus 23 pl7 i/o general-purp ose port l7 ? ? 5 37 a1 ? ? ? xd24 i/o external data bus 24 pm0 i/o general-purp ose port m0 ? ? 5 36 a2 ? ? ? xd25 i/o external data bus 25 pm1 i/o general-purp ose port m1 ? ? 5 35 b2 ? ? ? xd26 i/o external data bus 26 pm2 i/o general-purp ose port m2 ? ? 5 33 d4 ? ? ? xd27 i/o external data bus 27 pm3 i/o general-purp ose port m3 ? ? 5 32 b3 ? ? ? xd28 i/o external data bus 28 pm4 i/o general-purp ose port m4 ? ? 5 31 a4 ? ? ? xd29 i/o external data bus 29 pm5 i/o general-purp ose port m5 ? ? 5 29 c5 ? ? ? xd30 i/o external data bus 30 pm6 i/o general-purp ose port m6 ? ? 5 28 a5 ? ? ? xd31 i/o external data bus 31 pm7 i/o general-purp ose port m7 ? ? 5 27 b4 ? ? ?
fedl67q4060-0 ml67q4060/61/50/51 17/37 lapis semiconductor table 1-1 (6/6) list of pin functions of the ML67Q4050/ml67q4060 series that is provided below are applicable to the ML67Q4050 series only. table 1-1 list of ml 67q4050/ml67q4060 series pin functions (6 of 6) primary function secondary function tertiary function setting at reset pin assignment pin name i/o description signal name i/o description signal name i/o description signal name i/o description ipu schmitt trigger circuit sink current [ma] 144 qfp 144 bga 64 qfp 84 bga 64 wcsp romcs_n o external rom chip enable pn0 i/o general-purp ose port n0 ? ? 5 107 m12 ? ? ? ramcs_n o external ram chip enable pn1 i/o general-purp ose port n1 ? ? 5 105 k10 ? ? ? iocs0_n o external io0 chip enable pn2 i/o general-purp ose port n2 ? ? 5 104 m11 ? ? ? iocs1_n o external io1 chip enable pn3 i/o general-purp ose port n3 ? ? 5 103 n10 ? ? ? bs0_n o external byte select 0 pn4 i/o general-purp ose port n4 ?? 5 97n8 ??? bs1_n o external byte select 1 pn5 i/o general-purp ose port n5 ? ? 5 109 n13 ? ? ? bs2_n o external byte select 2 pn6 i/o general-purp ose port n6 ? ? 5 111 l11 ? ? ? bs3_n o external byte select 3 pn7 i/o general-purp ose port n7 ? ? 5 113 k11 ? ? ? oe_n o external data output enable po0 i/o general-purp ose port o0 ? ? 5 108 n12 ? ? ? wr_n o external write pulse po1 i/o general-purp ose port o1 ?? 5 98k9 ??? exbuse i/o general-purpose port o2 exbu se i external bus enable *note ?? 3 82n5 ??? exirome i/o general-purpose port o3 exiro me i external memory access enable ? ? 3 100 n9 ? ? ? boot1 i/o general-purpose port o4 boot 1 i boot select 1 ? ? 3 102 l10 ? ? ? *note: when setting exbuse to ?l?, do not use exirome and boot1 as general-purpose ports.
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 18/37 circuit types of pins t he following shows simplified circuits of pins of the ML67Q4050/ml67q4060 series. table 1-2 circuit type of each pin (1 of 2) circuit type pin name type 1 sysclk_p, rtcclk_p, test1, test2, bootclk type 2 resetn, type 3 sysclk_n, rtcclk_n, type 4 pd0, pd1, pd2, pd3 pa3, pa5, rstout_n, pb0, pb1, pb2, pb3, pc0, pc1, pc4, pc5, pd4, pe0, pe1, pe2, pe3, pe4, pf0, pf1, pf2, pf3, pf4, pf5, type 5 functions for the ML67Q4050 series. exbuse, exirome, boot1, xa0, xa1, xa2, xa3, xa4, xa5, xa6, xa7, xa8, xa9, xa10, xa11, xa12, xa13, xa14, xa15, xa16, xa17, xa18, xa19, xa20, xa21, xa22, romcs_n, ramcs_n, iocs0_n, iocs1_n, bs0_n, bs1_n, bs2_n, bs3_n, oe_n, wr_n pa1, pa2, type 6 functions for the ML67Q4050 series. xd0, xd1, xd2, xd3, xd4, xd5, xd6, xd7, xd8, xd9, xd10, xd11, xd12, xd13, xd14, xd15, xd16, xd17, xd18, xd19, xd20, xd21, xd22, xd23, xd24, xd25, xd26, xd27, xd28, xd29, xd30, xd31 type 7 pb4, pb5, pc2, pc3, pc6, pc7, pe5, pe6 type 8 pa0, pa4
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 19/37 table 1-2 circuit type of each pin (2 of 2) type 1 type 5 type 2 type 6 type 3 type 7 type 4 type 8 in out in/ out in/ out schmitt trigger circuit 50 k ? in schmitt trigger circuit in/ out 50 k ? in/ out ch select in/ out 50k ? schmitt trigger circuit
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 20/37 functional description cpu ? 32-bit risc cpu (arm7tdmi) ? little endian format ? maximum operating frequency of 33.333 mhz ? instruction structure: enables mixed execution of high-density 32-bit long instructions and the subset of them, i.e., 16-bit long instructions of high object efficiency. ? general-purpose registers: 32 bits x 31 registers ? built-in barrel shifter (operations of alu and barrel shift can be executed by a single instruction) ? built-in debug function (jtag interface) jtag interface pin is shared with gpio. internal memory ? 16kb ram processor bus connection ? 8kb bootrom ahb connection ? built-in flash rom processor bus connection of the 128kb(ml67q4051 and ml67q4061) or 64kb (ML67Q4050 and ml67q4060) ? flash rewrite count: 100 (max) ? p lat-external memory controller (func tion for the ML67Q4050 series only) ? setting of programmable access timing for each space ? rom (flash) access function supports 1-bank ? 8-mbyte rom space supports 16-bit and 32-bit devices supports flash memories supports page access ? sram access function 1-bank ? 8-mbyte sram space supports 16-bit, and 32-bit devices supports asynchronous srams ? external i/o access function 2-bank i/o space supports 8-bit, 16-bit, and 32-bit devices address setup, re/we pulse and data off timing can be set in one cycle units. ? p lat-interrupt controller/ex tended interrupt controller ? fiq: 1 source (nmi pin) ? irq: 31 sources (40 sources for the ML67Q4050 series) ? seven levels of interrupt priorities can be set for each interrupt source. ? p lat-system timer ? 16-bit auto-reload timer: ? 1ch ? p lat-sio (uart) ? full-duplex start-stop synchronization method ? built-in baud rate generator
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 21/37 dma controller ? ? 2ch ? multiple dma transfer request sources can be assigned for each channel. ? fixed mode or round robin mode can be selected for the priority order of channels. ? cycle still mode or burst mode can be se lected as the bus right request method. ? two types of dma transfer requests are supported: software request and external request. ? maximum number of transfers: 65,536 transfers ? data transfer size: 8/16/32 bits ? transfer request source: i2s i2c uart spi (external dma requests are handled by the ML67Q4050 series only.) watchdog timer ? 1 6-bit timer ? maximum overflow time is 8.94 seconds (when operating at 30 mhz apb clock) ? watchdog timer mode provided ? interrupts or resets are generated according to settings. ? an ?asserted? period can be set for reset signal output (rstout_n). ? the wdtovf_n pin outputs a l level at power-on reset ? starting/stopping a watchdog timer ? clearing a watchdog occurrence factor ? the watchdog timer cycle can be changed during watchdog timer operation. a/d converter ? 10-bit sequential comparison type ? 4ch ? sample hold function ? conversion time: 20 ? s (max 50ksample/s) ? enables sequential a/d conversion (one-time/continuous) from the minimum channel to the maximum channel selected arbitrarily. ? dnl (max.) = ? 6.0 lsb ? inl (max.) = ? 6.0 lsb ? zero-scale error (max.) = ? 8.0 lsb ? full-scale error (max.) = ? 8.0 lsb i2c bus controller ? philips i2c bus specification ver 2.1 conformed controller ? supports multi-master mode. ? data transfer modes standard mode (100 khz) fast mode (400 khz) ? 7-bit/10-bit address compatible ? clocks are stopped to synchronize data between master and slave. ? supports dma transfer. flexible timer ? 1 6-bit timer ? 6ch ? operation mode operable in each of the modes, auto reload ti mer (art)/compare out (cmo)/pulse width modulation (pwm)/capture (cap)
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 22/37 rtc ? generates 1 second from 32.768 khz ? built-in 32-bit counter that counts 32 bits by 1-second clock ? 32-bit compare interrupt function i2s transmit/receive ? connection interface for general-purpose dacs/adcs. conforms to philips i2s (the inter-ic sound) specification. ? 3-wire interface of word clock (ws), bit clock (sck) and serial data (sd) ? the audio reference clock is generated from the main clock. ? channel data length: 16/18/20/24 bits (cpu interface: 16 bits) ? word clock length: 32/64 fs ? supports master/slave ? enables the settings of 1-bit delay on or off and left or right inversion. ? 256 ? 16 bit fifo shared betwee n transmission and reception ? supports dma transfer. ? audio_clk output possible gpio ? built-in gpio of 8 bits ? 1ch, 7 bits ? 2ch, and 6 bits ? 3ch (in the ML67Q4050 series, 8 bits ? 8ch, 7 bits ? 3ch, 6 bits ? 3ch, and 5 bits ? 1ch) ? input or output can be specified for each bit. every bit can be configured as interrupt input. ? interrupt function (level/edge and positive logic/negative logic can be set, and this function is also supported even when no clock is operating.) ? three 20 ma sink pins uart ? two channels of serial communication function with fifo ? serial communication with 16-byte fifo ? flow control by hardware ? dma transfer support spi ? built-in two channel of full duplex serial peripheral interface ? the master or slave mode can be selected. ? built-in 16-byte or 16-word (16-bit) fifo on the transmitting side and receiving side ? 8 bits (byte) or 16 bits (word) can be selected as the transfer size. ? supports dma transfer. ? built-in baud rate generator clock ? main clock oscillator (16 to 33.333mhz) ? rtc clock oscillator (32.768khz clock) ? ring oscillator
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 23/37 power management ? p ower saving mode cpu halt mode: stops only the cpu clock. stop mode: stops all the clocks of the chip except rtc. ? clock operation or stop can be set for each block. ? variable system clock frequencies package ? ml 67q4060/ml67q4061 64-pin tqfp (tqfp64-p-1010-0.50-k) 84-pin lfbga (p-lfbga84-0909-0.80) (8 pins are not connected.) 64-pin wcsp (p-vfbga64-5.09 ? 4.84-0.50-w, p-vflga64-5.09 ? 4.84-0.50-w) ? ML67Q4050 144-pin lqfp (lqfp144-p-2020-0.50-zk) ? ml67q4051 144-pin lqfp (lqfp144-p-2020-0.50-zk) 144-pin lfbga (p-lfbga144-1111-0.80)
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 24/37 absolute maximum ratings parameter symbol condition rating unit digital power supply voltage (core) v dd_core ? 0.3 to +3.6 digital power supply voltage (i/o) v dd_io ? 0.3 to +4.6 input voltage v i ? 0.3 to v dd_io +0.3 output voltage v o ? 0.3 to v dd_io +0.3 pll section power supply voltage (pll) v dd_pll ? 0.3 to +3.6 v allowable input current i i ? 10 to +10 ?h? allowable input current i oh +10 ?l? allowable input current i ol gnd = 0 v ta = 25 ?c ? 20 ma power dissipation p d ta = 85 ?c per package 530 mw 144pin lqfp (lqfp144-p-2020-0.50-zk) -55 to +150 144pin lfbga (p-lfbga144-1111-0.80) -55 to +150 64pin qfp (tqfp64-p-1010-0.50-k) -55 to +150 84pin lfbga (p-lfbga84-0909-0.80) -55 to +125 storage temperature t stg 64pin wcsp (p-vfbga64-5.09 x 4.84-0.50-w, p-vflga64-5.09 x 4.84-0.50-w) -55 to +150 ?c
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 25/37 recommended operating conditions (gnd = 0 v) parameter symbol condition min. typ. max. unit digital power supply voltage (core) v dd_core 2.25 2.5 2.75 digital power supply voltage (i/o; when external memory bus is not used) v dd_co re 3.3 3.6 digital power supply voltage (i/o; when external memory bus is used) v dd_io 3.0 3.3 3.6 pll section power supply voltage (pll) v dd_pll ? 2.25 2.5 2.75 v cpu operating frequency f osc ? 0.032 ? 33.333 mhz ambient temperature ta ? ? 40 25 85 ?c
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 26/37 electrical characteristics dc characteristics (v dd_core = 2.25 to 2.75 v, v dd_io = 3.0 to 3.6 v, ta = ? 40 to +85 ?c) parameter symbol condition min. typ. max. unit ?h? input voltage v ih 2.0 ? v dd_io + 0.3 ?l? input voltage v il ? 0.3 ? 0.8 v t+ ? ? v dd_io ? 0.7 schmitt trigger input threshold voltage v t- v dd_io ? 0.2 ? ? schmitt hysteresis v hys ? v dd_io ? 0.1 ? ? 3ma buffer *2 i oh = ? 3 ma 5ma buffer *2 i oh = ? 5 ma ?h? output voltage 20ma buffer *1 v oh i oh = ? 20 ma 2.4 ? ? 3ma buffer *2 i ol = 3 ma 5ma buffer *2 i ol = 5 ma ? ? 0.4 ?l? output voltage 20ma buffer *1 v ol i ol = 20 ma ? ? 0.45 v input leakage current *4 v i = 0v / v dd_io ? 10 ? 10 input leakage current *3 i ih /i il v i = 0v pull-up resistor 50 k ? ? ? 200 output leakage current i lo v o = 0v / v dd_io ? 10 ? 10 ua (v dd_core = 2.25 to 2.75 v, v dd_io = v dd_core to 2.75 v, ta = ? 40 to +85 ?c) parameter symbol condition min. typ. max. unit ?h? input voltage v ih 1.7 ? v dd_io +0.3 ?l? input voltage v il ? 0.3 ? 0.7 v t+ ? ? v dd_io ? 0.7 schmitt trigger input threshold voltage v t- v dd_io ? 0.2 ? ? schmitt hysteresis v hys ? v dd_io ? 0.1 ? ? 3ma buffer *2 5ma buffer *2 ?h? output voltage 20ma buffer *1 v oh i oh = ? 1 ma 2.0 ? ? 3ma buffer *2 5ma buffer *2 i ol = 1 ma ? ? 0.4 ?l? output voltage 20ma buffer *1 v ol i ol = 20 ma ? ? 0.5 v input leakage current *4 v i = 0v / v dd_io ? 10 ? 10 input leakage current *3 i ih /i il v i = 0v pull-up resistor 50 k ? ? ? 150 output leakage current i lo v o = 0v / v dd_io ? 10 ? 10 ua
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 27/37 (v dd_core = 2.25 to 2.75 v, v dd_io = 2.75 to 3.0 v, ta = ? 40 to +85 ?c) parameter symbol condition min. typ. max. unit ?h? input voltage v ih 2.0 ? v dd_io +0.3 ?l? input voltage v il ? 0.3 ? 0.8 v t+ ? ? v dd_io ? 0.7 schmitt trigger input threshold voltage v t- v dd_io ? 0.2 ? ? schmitt hysteresis v hys ? v dd_io ? 0.1 ? ? 3ma buffer *2 5ma buffer *2 ?h? output voltage 20ma buffer *1 v oh i oh = ? 1 ma 2.4 ? ? 3ma buffer *2 5ma buffer *2 i ol = 1 ma ? ? 0.4 ?l? output voltage 20ma buffer *1 v ol i ol = 20 ma ? ? 0.45 v input leakage current *4 v i = 0v / v dd_io ? 10 ? 10 input leakage current *3 i ih /i il v i = 0v pull-up resistor 50 k ? ? ? 175 output leakage current i lo v o = 0v / v dd_io ? 10 ? 10 ua
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 28/37 (v dd_core = 2.25 to 2.75 v, v dd_io = v dd_core to 3.6v,ta = ? 40 to +85 ?c) parameter symbol power type condition min. typ. max. unit pin capacitance 1 *6 c 1 ? ? ? 5 ? pin capacitance 2 *5 c 2 ? ? ? 9 ? pin capacitance 3 *1 c 3 ? ? ? 18 ? pf ta = 85 ?c v dd_core = 2.75v ? ? 485 i dds_core core ta = 25 ?c v dd_core = 2.5v ? 10.131 ? ta = 85 ?c v dd_io = 3.6v ? ? 10 i dds_io *7 io ta = 25 ?c v dd_io = 3.3v ? 0.062 ? ta = 85 ?c v dd_pll = 2.75v ? ? 5 current consumption (at stop) i dds_pll pll ta = 25 ?c v dd_pll = 2.5v ? 0.027 ? ua ? ? 30 i ddh_core core ? 25 ? ? ? 16 i ddh_io io ? 13.78 ? ? ? 14 i ddh_pll pll ML67Q4050/51 f osc = 33.333 mhz no load ? 6.56 ? ? ? 30 i ddh_core core ? 25 ? ? ? 16 i ddh_io io ? 8.49 ? ? ? 14 current consumption (at halt) i ddh_pll pll ml67q4060/61 f osc = 33.333 mhz no load ? 6.56 ? ? ? 76.00 i ddo_core core ? 49.90 ? ? ? 30.00 i ddo_io io ? 13.78 ? ? ? 14.00 i ddo_pll pll ML67Q4050/51 f osc = 33.333 mhz no load ? 6.56 ? ? ? 76.00 i ddo_core core ? 49.90 ? ? ? 30.00 i ddo_io io ? 8.49 ? ? ? 14.00 current consumption (dynamic) *8 i ddo_pll pll ml67q4060/61 f osc = 33.333 mhz no load ? 6.56 ? ma applicable pins: *1: 20ma sink pins *2: pins other than the 20ma sink pins *3: pins with a 50 k ? pull-up resistor *4: pins without a 50 k ? pull-up resistor *5: ain pin *6: pin other than the ain pin and 20ma sink pins *7: input ports: v dd_io or 0v. other ports: no load. *8: the following lists typical operating cyrrent of each operating frequency.
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 29/37 reference: the reference of the consumption current value when the mcu is operating the following tables are reference data of consumptio n current (iddo) of ml67q4060/50 series at the time of operation. this figure changes with the circumference function to be used or its conditions of operation. ? typical operating cyrrent of each operating frequency for ML67Q4050/51 frequency [mhz] power type condition 8 12 16 20 24 28 33.333 core v dd_core = 2.5v 21.80 26.19 30.59 34.98 39.38 43.78 49.90 io v dd_io = 3.3v 4.69 6.23 7.76 9.30 10.83 12.37 13.78 pll v dd_pll = 2.5v 3.29 3.64 4.00 4.50 5.15 5.80 6.56 total ? ta = 25?c 29.78 36.06 42.35 48.78 55.36 61.94 70.23 note: the values shown above are references. use these values as reference when using this lsi. ? typical operating cyrrent of each operating frequency for ml67q4060/61 frequency [mhz] power type condition 8 12 16 20 24 28 33.333 core v dd_core = 2.5v 21.80 26.19 30.59 34.98 39.38 43.78 49.90 io v dd_io = 3.3v 2.89 3.84 4.78 5.73 6.67 7.62 8.49 pll v dd_pll = 2.5v 3.29 3.64 4.00 4.50 5.15 5.80 6.56 total ? ta = 25?c 27.97 33.67 39.37 45.21 51.20 57.19 64.94 note: the values shown above are references. use these values as reference when using this lsi.
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 30/37 package dimensions 144-pin lqfp (lqfp144-p-2020-0.50-zk) (unit: mm) lqfp144-p-2020-0.50-zk package material lead frame material pin treatment package weight (g) rev. no./last revised epoxy resin 42 alloy solder plating ( 5 m) 1.37 typ 5/nov. 28, 1996 notes for mounting the surface mount type package the surface mount type packages are very susceptible to he at in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact rohm?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 31/37 144-pin lfbga (p- lfbga144-1111-0. 80) (unit: mm) p-lfbga144- 1111-0.80 package material epoxy resin ball material sn/pb package weight (g) 0.30 typ. 5 rev. no./last revised 1/aug. 25, 1999 notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact rohm?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 32/37 64-pin tqfp (tqfp64-p-1010-0.50-k) (unit: mm) tqfp64-p-1010-0.50-k mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5 m) package weight (g) 0.26 typ. 5 rev. no./last revised 4/oct. 28, 1996 notes for mounting the surface mount type package the surface mount type packages are very susceptible to he at in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact rohm?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 33/37 84-pin lfbga (p-lfbga84-0909-0.80) (unit: mm) p-lfbga84-0909-0.80 package material epoxy resin ball material sn/pb package weight (g) 0.20 typ. 5 rev. no./last revised 1/may 15, 2000 notes for mounting the surface mount type package the surface mount type packages are very susceptible to he at in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact rohm?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 34/37 64-pin wcsp (p-vfbga64-5.09 ? 4.8 4-0.50-w) (unit: mm) p-vfbga64-5.09x4.84-0.50-w package material epoxy resin ball material sn/ag/cu package weight (g) typ. 5 rev. no./last revised notes for mounting the surface mount type package the surface mount type packages are very susceptible to he at in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact rohm?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 35/37 64-pin wcsp (p-vflga64-5.09 ? 4.8 4 -0.50-w) (unit: mm) s b 0.20 p-vflga64-5.09x4.84-0.50-w notes for mounting the surface mount type package the surface mount type packages are very susceptible to he at in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact rohm?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 36/37 revision history page document no. date previous edition current edition description fedl67q4060-01 jan.21, 2008 ? ? final edition 1
fedl67q4060-01 lapis semiconductor ml67q4060/61/50/51 37/37 notice no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing lapis semiconductor's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-a utomation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the pr escribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a me dical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2008 - 2011 lapis semiconductor co., ltd.

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